power
Low-Power Design
Low-Power
Digital Multiplier
Architected an energy-efficient digital multiplier using Cadence Virtuoso with transistor-level optimization to minimize leakage power for neural network accelerators. Implemented advanced power-reduction techniques including clock gating and multi-Vt optimization.
Virtuoso
GPDK090
Power Analysis
DRC/LVS
info
Project Overview
Designed an energy-efficient digital multiplier optimized for low-power applications in neural network accelerators. Implemented using advanced power-reduction techniques including clock gating, multi-threshold voltage (multi-Vt) optimization, and supply voltage scaling for minimal leakage power consumption.
speed
Performance
- Reduced Switching Activity
- Optimized Critical Path
- Efficient Gate Design
- Minimal Leakage Current
savings
Power Optimization
- Clock Gating Techniques
- Multi-Vt Devices
- Supply Voltage Scaling
- Layout Optimization
build
Technologies & Tools
Cadence
GPDK090
DRC/LVS
Power Analysis