Project Overview
This ASIC project presents a fully-functional RISC-V processor with complete instruction set architecture support, integrated peripheral controllers, and comprehensive testbenches. Features modular datapath design, control unit, ALU, register file, and UART serial interface for embedded applications.
Performance Metrics
computer
Clock Frequency
100 MHz
target operating speed
memory
Instruction Width
32-bit
RISC-V base ISA
verified
Register File
32 x 32-bit
dual-port design
Design Specifications
architecture Core Architecture
- • 5-stage pipeline: Fetch, Decode, Execute, Memory, Writeback
- • Datapath modules: ALU, register file, memory interface
- • Control unit: Instruction decode and microcode generation
- • Full ISA support: RV32I base instruction set
engineering Verification & Integration
- • UART controller: Serial communication interface
- • Directed testbenches: Comprehensive instruction testing
- • RTL synthesis: Gate-level implementation verified
- • Post-synthesis validation: SDF-annotated simulation
Tools & Technologies
Verilog HDL
Synopsys VCS
Design Compiler
RISC-V ISA
Testbench Framework
Access Full Documentation
Download comprehensive design documentation including RTL source code, testbenches, synthesis results, and verification reports with detailed performance analysis.
file_download Download Full Report (PDF)