Project Overview
This project showcases a comprehensive design of a 4-bit array multiplier implemented at the transistor level using hierarchical construction with inverter, NAND, and XOR gates. The design demonstrates advanced VLSI techniques including full-custom layout development with stringent design rule checking (DRC) and layout versus schematic (LVS) verification using GPDK090 technology.
Performance Metrics
bolt
Power Efficiency
2 pJ
per operation
straighten
Circuit Area
~2086 µm²
full-custom layout
verified
Technology Node
GPDK090
90nm PDK
Design Specifications
architecture Hierarchical Architecture
- • 4-bit operands: 16-bit partial product generation
- • Modular gates: Optimized inverter, NAND, and XOR cells
- • Layout methodology: Stick diagram to full-custom design
- • Verification: DRC and LVS clean at 0.0 violations
engineering Advanced Techniques
- • Parasitic extraction: High-accuracy RC parasitic analysis
- • Device optimization: W/L ratio tuning for performance
- • Layout analysis: Current density and thermal considerations
- • Power integrity: Optimized power distribution network
Tools & Technologies
Cadence Virtuoso
CMOS GPDK090
DRC/LVS Verification
Full-Custom Layout
Parasitic Extraction
Access Full Documentation
Download the comprehensive project report including detailed design methodology, simulation results, layout analysis, and verification documentation.
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