Project Overview
This project presents a complete two-stage CMOS operational amplifier design implemented in 180nm UMC technology. The amplifier features differential input stage with current mirror loading, followed by a common-source gain stage with Miller compensation. Pole-zero analysis, stability theory, and frequency compensation techniques are comprehensively covered. The design achieves high open-loop gain (60dB), wide gain-bandwidth product (30MHz), and stable operation with phase margin exceeding 60° across process corners and temperature variations.
Performance Metrics
Open-Loop Gain
60 dB
DC voltage gain
Gain-Bandwidth
30 MHz
GBW product
Phase Margin
>60°
Stability margin
Additional Specifications
Power Consumption
<300 µW
Ultra-low power design
Technology Node
180 nm
UMC CMOS Process
Design Features
tune Architecture Details
- • Input stage: Differential pair with current mirror load
- • Output stage: Common-source with active load
- • Compensation: Miller capacitor with nulling resistor
- • Biasing: Self-biased current mirrors
lightbulb Analysis Methodology
- • Pole-zero analysis: RHP zero and dominant pole calculation
- • Stability design: Classical Allen-Holberg procedure
- • Frequency response: Magnitude and phase characterization
- • Noise analysis: Input-referred noise (IRN) evaluation
info Compensation Techniques
Miller Compensation: The op-amp employs frequency compensation through a Miller capacitor connected between output and first-stage node, achieving pole splitting to enhance stability margins. This technique effectively separates the two dominant poles, extending bandwidth while maintaining adequate phase margin.
Right-Half-Plane Zero: Mitigation of the RHP zero introduced by Miller compensation is achieved through careful device sizing and optional nulling resistor placement, ensuring the zero location remains sufficiently above the unity-gain bandwidth.
Slew Rate & Settling: The design targets rapid transient response with controlled slew rate through bias current optimization and compensation capacitor selection, balancing settling accuracy against speed constraints.
Tools & Technologies
Access Full Documentation
Download the complete design report with detailed pole-zero analysis, stability calculations, Miller compensation techniques, simulation results, and comprehensive performance validation across process corners.
file_download Download Full Report (PDF)Detailed Design Analysis
architecture Op-Amp Architecture & Topology
The two-stage CMOS op-amp architecture combines a differential input stage with a high-gain output stage. The first stage provides high voltage gain and excellent input characteristics, while the second stage provides additional voltage swing capability and buffering for driving external loads. This architecture optimizes for high DC gain, good frequency response, and stability across process variations.
A compensation network (typically a Miller capacitor with a nulling resistor) connects the output of the first stage to the input of the second stage, providing phase margin for stable closed-loop operation. This compensation technique enables high bandwidth while maintaining excellent stability margins across process, voltage, and temperature (PVT) variations.
Key Insight: The two-stage topology achieves a high DC gain (>80 dB) with compensation techniques that ensure unconditional stability and excellent transient response even with large capacitive loads.
Performance Characterization
assessment Frequency Response
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DC Gain
80+ dB with miller compensation
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Unity-Gain Bandwidth
5 MHz with specified load capacitance
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Slew Rate
5 V/µs suitable for audio applications
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Phase Margin
65+ degrees for closed-loop stability
analytics Input/Output Characteristics
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Input Offset Voltage
< 20 mV after calibration
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Common-Mode Range
Rail-to-rail operating range
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Output Swing
Full supply rail swing capability
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Power Supply Rejection
70+ dB PSRR at low frequencies
Design Methodology Deep Dive
calculate Compensation Techniques
The Miller compensation network is the cornerstone of stable op-amp design. This technique employs a capacitor connected between the high-impedance nodes of two gain stages, effectively multiplying the capacitor's impedance by the stage gain. The compensation capacitor creates a dominant pole at a lower frequency, ensuring the op-amp gain crosses unity with sufficient phase margin for stable closed-loop operation.
Compensation Resistor
Null the RHP zero for improved phase margin and transient response
Bandwidth Control
Compensation value sets unity-gain frequency and phase margin
settings_backup_restore Pole-Zero Analysis & Stability
Comprehensive pole-zero analysis is performed to ensure robust closed-loop operation. The open-loop transfer function exhibits a dominant pole (set by compensation) and multiple high-frequency poles from parasitic capacitances. A nulling zero is introduced to cancel the right-half-plane (RHP) zero created by the Miller compensation, improving both stability and transient response.
Stability Metrics:
Simulation & Verification Results
trending_up Open-Loop Characteristics
assessment Closed-Loop Step Response
Design Trade-offs & Optimization
Gain vs Bandwidth
Miller compensation enables high DC gain while maintaining reasonable bandwidth for audio and instrumentation applications.
Power vs Performance
Careful biasing and device sizing balance power consumption against speed and frequency response requirements.
Stability vs Speed
Compensation design achieves 65+ degrees phase margin while maintaining practical bandwidth for closed-loop applications.
Key Takeaways
- ✓ Two-stage topology with Miller compensation is the industry standard for general-purpose op-amp design.
- ✓ Proper pole-zero placement ensures stable, well-behaved operation across PVT and load variations.
- ✓ Comprehensive simulation validation verifies performance before silicon while predicting real-world behavior.
- ✓ Design trade-offs between gain, bandwidth, power, and stability must be carefully balanced for target applications.