I am Zailesh A R, an M.Tech student in VLSI Design with a strong focus on integrated circuit development. I am interested in Low Power Design, Digital IC Design & ASIC Design using industry-standard EDA tools, with hands-on experience in RTL design, synthesis, timing analysis, and custom CMOS design.
Specializing in advanced Digital and Analog IC design, low-power architectures, and verification methodologies.
Spearheaded the design and debugging of embedded circuits and firmware. Gained hands-on experience with ESP-based IoT prototypes and end-to-end product development for commercial applications.
Graduated with distinction (CGPA 8.06). Focused on embedded systems and semiconductor fundamentals.
Explore my recent works here, click on the view report card to view detailed reports and insights into my design process, methodologies, and outcomes.
Designed a complete 4-bit array multiplier at transistor level using hierarchical construction with inverter, NAND, and XOR gates. Achieved full-custom layout with DRC/LVS-clean verification in GPDK090, consuming 2 pJ per operation with a final area of ~2086 µm².
Implemented a 4-bit non-restoring square root algorithm in synthesizable Verilog with comprehensive verification. Deployed on DE2-115 FPGA with timing closure achieving 2.28 ns setup slack and 0.24 ns hold slack.
Designed synthesizable Verilog RTL architecture with functional verification using Synopsys VCS. Performed synthesis using Design Compiler and validated equivalence with Formality.
Engineered a modular RISC-V processor with datapath, control unit, ALU, and UART controller. Verified functionality using directed testbenches and performing RTL synthesis with Synopsys Design Compiler.
Designed a high-gain telescopic CMOS operational amplifier with enhanced swing and stability. Optimized biasing networks and transistor sizing (W/L) through analytical modeling in Cadence Virtuoso to achieve superior gain-bandwidth product and phase margin performance.
Advanced 3D TCAD simulation of FinFET and GAFET devices at 3-5nm technology nodes with comprehensive analysis of gate architecture, carrier transport, and performance metrics.
Comprehensive DC and transient TCAD simulation of nMOS and pMOS devices across technology nodes with full physics analysis including short-channel effects and leakage mechanisms.
High-gain, high-bandwidth amplifier utilizing cascoded MOSFET stages optimized through gm/ID and PDM methodologies for superior output impedance and enhanced frequency response characteristics.
Miller-compensated operational amplifier designed for high open-loop gain (60dB), wide bandwidth (30MHz), and stable operation with comprehensive frequency compensation and pole-zero analysis techniques.
Detailed TCAD analysis of Metal-Oxide-Semiconductor capacitor structures with C-V characterization, interface defect extraction, and oxide quality assessment across operating regions.
Complete TCAD simulation of PN junction diodes with I-V characterization, temperature effects, and analysis of carrier transport mechanisms including generation-recombination and breakdown.
An advanced home automation ecosystem featuring multi-feed sensor integration and real-time cloud synchronization. Designed a custom PCB with ESP32, integrating voice commands via Alexa/Google Assistant and a Flutter-based mobile dashboard for seamless control.
Architected a high-speed digital multiplier using Cadence Virtuoso with transistor-level optimization to minimize leakage power for neural network accelerators.
Developed a wearable cooling prototype utilizing Peltier modules and custom control circuits for chemotherapy patients, preventing alopecia through precise thermal regulation.
Designed a parameterized memory module with read/write operations in Verilog. Validated timing and functionality on a Cyclone IV FPGA platform.
Demonstrated leadership, organizational skills, and extracurricular excellence.
Led content strategy and managed creative teams to produce high-impact digital content, enhancing the organization's brand presence across multiple platforms.
Oversaw content creation and distribution for student branch activities, ensuring consistent messaging and engagement with the student community.
Bridged the gap between student members and industry professionals, facilitating effective communication for workshops and technical events.
Authored technical articles, event reports, and social media copy, contributing to the consistent documentation of the cell's activities.
Created engaging content for newsletters and event promotions, helping to increase student participation in IEEE initiatives.
Drafted diplomatic content, background guides, and promotional materials for Model United Nations conferences.
Led strategic planning and execution for the event, managing schedules, logistics, and team coordination to ensure a seamless experience.
Coordinated core activities for MAGIC 2.0, overseeing volunteer management and event logistics.
Active member of the Free and Open Source Software cell, promoting open-source technologies and organizing workshops.
Participated as a delegate, engaging in diplomatic debates and resolution drafting on global issues.
Recognized for innovative working models in electronics and sustainable energy at various science fairs.